EDN

VHDL-AMS simulation for battery chargers

The Maxim 2003, and a parameterized NiCd battery model, were created using the VeriBest behavioural modelling language DIABLO. Although many SPICE simulators nowadays provide some high-level modelling ...
Ars Technica

VHDL / HDL compiler and simulator

A question for any CpE/EE/CS students/grads out there: I am currently using Altera Max-Plus II, but on my windows box only because that is all it supports. However I was wondering if there are any ...
EDN

Ansoft approves VHDL-AMS models for use with simulator

Ansoft reports that it has certified the VHDL-AMS models from the FAT-AK30 working group of the German Association of the Automotive Industry (Verband der Automobilindustrie, VDA) to run in Simplorer, ...
Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
Design-Reuse

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...